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AD5381
TIMING CHARACTERISTICS
SERIAL INTERFACE TIMING
Table 6. DV
DD
= 2.7 V to 5.5 V; AV
DD
= 4.5 V to 5.5 V or 2.7 V to 3.6 V; AGND = DGND = 0 V; all specifications
T
MIN
to T
MAX
, unless otherwise noted
Parameter
1
,
2
,
3
Limit at T
MIN
, T
MAX
Unit
t
1
33
ns min
t
2
13
ns min
t
3
13
ns min
t
4
13
ns min
t
5
4
13
ns min
t
6
4
33
ns min
t
7
10
ns min
t
7A
50
ns min
t
8
5
ns min
t
9
4.5
ns min
t
104
30
ns max
t
11
670
ns max
t
124
20
ns min
t
13
20
ns min
t
14
100
ns max
t
15
0
ns min
t
16
100
ns min
t
17
8
μs typ
t
18
20
ns min
t
19
12
μs max
t
205
20
ns max
t
215
5
ns min
t
225
8
ns min
t
23
20
ns min
Rev. A | Page 8 of 36
Description
SCLK cycle time
SCLK high time
SCLK low time
SYNC falling edge to SCLK falling edge setup time
24
th
SCLK falling edge to SYNC falling edge
Minimum SYNC low time
Minimum SYNC high time
Minimum SYNC high time in Readback mode
Data setup time
Data hold time
24
th
SCLK falling edge to BUSY falling edge
BUSY pulse width low (single channel update)
24th SCLK falling edge to LDAC falling edge
LDAC pulse width low
BUSY rising edge to DAC output response time
BUSY rising edge to LDAC falling edge
LDAC falling edge to DAC output response time
DAC output settling time
CLR pulse width low
CLR pulse activation time
SCLK rising edge to SDO valid
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1
Guaranteed by design and characterization, not production tested.
2
All input signals are specified with t
r
= t
f
= 5 ns (10% to 90% of V
CC
) and are timed from a voltage level of 1.2 V.
3
See
Figur
,
, and
.
Figure 2,
e 3 Figure 4
Figure 5
4
Standalone mode only.
5
Daisy-chain mode only.
C
50pF
TO OUTPUT PIN
V
OH
(MIN) OR
V
OL
(MAX)
200
μ
A
200
μ
A
I
OL
I
OH
0
Figure 2. Load Circuit for Digital Output Timing
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